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Federal Circuit Affirms Summary Judgment Of Non Infringement For Failure To Prove Structural Equivalence Under § 112(f)
03/03/2026On February 19, 2026, the U.S. Court of Appeals for the Federal Circuit affirmed the District of Delaware’s grant of summary judgment of non infringement in favor of defendants in Genuine Enabling Tech. LLC v. Sony Corp., No. 17-CV-135, 2024 WL 1255513 (D. Del. Mar. 25, 2024). The Federal Circuit held that patentee failed to present sufficient evidence that the accused components were structurally equivalent to the disclosed structure of a means plus function limitation under 35 U.S.C. § 112(f).
Patentee filed suit against defendants in February 2017, alleging infringement of U.S. Patent No. 6,219,730 (“730 Patent”). At the time of the invention, computers supported multiple user input devices, including keyboards, mouse, microphone, and pen based devices. Each input device required dedicated system resources (e.g., its own port), which created practical limitations given the limited resources. The ’730 Patent discloses a system that synchronizes multiple input streams from different input devices and encodes them into a single combined data stream for transmission.
With respect to the accused video game controllers and consoles, patentee alleged that the Bluetooth modules therein synchronize user inputs from controller buttons with input from controller sensors (e.g., accelerometers).
The district court concluded that the “encoding means for synchronizing” limitation was subject to means plus function treatment under § 112(f) because the claim language fails to recite sufficiently definite structure. The court construed the claimed function as synchronizing the user input stream with another input stream and encoding both into a combined data stream. The court then identified the corresponding structure as “the logic design at block 34 in Figure 4A and equivalents thereof.” No party disputed that logic block 34, as a whole, constituted the relevant disclosed structure.
Logic block 34 is depicted in the specification as a detailed logic circuit containing multiple components, including a clock generator, oscillator, and data selector. The specification describes a multi step synchronization process in which a bit rate clock is generated, input streams are clocked, and a data selector samples bits from each stream in order to produce a synchronized output.
Although patentee’s expert acknowledged that multiple components of logic block 34 played roles in synchronization, the expert ultimately narrowed his equivalence analysis to focus almost exclusively on the presence of a bit rate clock. Patentee did not obtain schematics or internal design documents for the accused Bluetooth modules during discovery, and its expert did not analyze the internal circuitry of the accused products. Instead, his opinions relied on general knowledge of Bluetooth protocols and the assumption that bit-clock synchronization rendered the accused products structurally equivalent. The district court excluded his ultimate opinion on structural equivalence, finding it unsupported and conclusory. The court emphasized that the expert failed to explain why most elements of logic block 34 could be disregarded or treated as insubstantial.
Defendants also moved for summary judgment of non infringement. The district court granted the motion, concluding that patentee lacked sufficient evidence to prove that the accused products performed the claimed function in substantially the same way as the disclosed structure. Patentee appealed both the exclusion of its expert’s testimony and the grant of summary judgment.
The Federal Circuit affirmed the district court’s decision. The Federal Circuit reiterated that literal infringement of a means plus function limitation requires proof that the accused structure performs the identical function and is identical or structurally equivalent to the disclosed structure, evaluated under the function way result test. While a component by component comparison is not required, the court emphasized that patentees must meaningfully account for the disclosed structure as a whole.
Here, logic block 34 was a detailed circuit with multiple interacting elements, yet patentee’s equivalence analysis focused on a single element—the bit rate clock—without explaining why the remaining components were immaterial. The Federal Circuit held that ignoring a significant portion of the disclosed structure defeats a showing of structural equivalence.
This decision reinforces the heightened evidentiary burden associated with means plus function claims. Where a patent discloses a detailed structure or circuit as the corresponding structure of a means-plus-function element, patentees must present evidence addressing that structure in its entirety or meaningfully explain why certain elements may be discounted. Selectively focusing on a single component—without justification—will not suffice.
